The present invention relates to a semiconductor memory device, and more particularly, to a data alignment circuit and a data alignment method in which data externally inputted in series are aligned in parallel for a prefetch operation.
In general, a synchronous memory device performs a prefetch operation in which data are externally inputted in series are aligned in parallel by a data strobe signal so that the data can be concurrently transmitted to a memory cell.
For example, when a 4-bit prefetch operation is performed, a conventional data alignment circuit includes seven latch units 10, 20, 30, 40, 50, 60, and 70 as shown in FIG. 1. Operations thereof will now be described in detail.
First, eight data are sequentially inputted as an input signal DIN. Then, the first four data of the eight data contained in the input signal DIN are aligned respectively in series through the latch unit 10 in response to the rising edge of the rising data strobe signal RDQS.
The four data aligned through the latch unit 10 are then aligned respectively through the latch unit 20 in response to the rising edge of the falling data strobe signal FDQS. These data are then outputted by the latch unit 20 as the data alignment signal DIN_EV1.
At this time, the rising data strobe signal RDQS corresponds to the rising edge of the data strobe signal DQS. The falling data strobe signal FDQS corresponds to the falling edge of the data strobe signal DQS.
Data contained in the alignment signal DIN_EV1 are also aligned respectively in series in response to the rising edge of the rising data strobe signal RDQS through the latch unit 30. Data aligned through the latch unit 30 are then aligned respectively in series through the latch unit 40 in response to the rising edge of the falling data strobe signal FDQS. Then, these data are finally outputted as a data alignment signal DIN_EV0.
Accordingly, the data alignment signal DIN_EV1 is shifted by one clock cycle 1tCK through the two latch units 30 and 40 based upon the falling data strobe signal FDQS; therefore, the data are outputted as the data alignment signal DIN_EV0.
Meanwhile, the remaining four data contained in the eight data of the input signal DIN are aligned respectively through the latch unit 50 in response to the rising edge of the falling data strobe signal FDQS. These remaining four data of the eight data are then outputted as the data alignment signal DIN_OD1.
These data contained in the data alignment signal DIN_OD1 are also aligned respectively in series through the latch unit 60 in response to the rising edge of the rising data strobe signal RDQS. These data aligned through the latch unit 60 are then aligned respectively in series through the latch unit 70 in response to the rising edge of the falling data strobe signal FDQS. These data are then finally outputted from the latch unit 70 as the data alignment signal DIN_OD0.
Accordingly, the data alignment signal DIN_OD1 is shifted (i.e., time delayed) by one clock cycle through the two latch units 60 and 70 in response to the falling data strobe signal FDQS. The data are then outputted as the data alignment signal DIN_OD0.
As a consequence of sequentially inputting the eight data through the seven latch units 10 to 70 of the data alignment circuit of FIG. 1, the data alignment signal DIN_EV1 corresponds to the first four data out of the eight data and the data alignment signal DIN_OD1 corresponds to the remaining four data of the eight data. As a result, the data alignment signal DIN_EV0 is time shifted relative to the data alignment signal DIN_EV1 by one clock cycle. As a result the data alignment signal DIN_OD0 is shifted relative to the data alignment signal DIN_OD1 by one clock cycle.
In other words, during a 4-bit prefetch operation, the conventional data alignment circuit concurrently outputs eight data, which are sequentially inputted, by aligning the data in parallel in a 4-bit unit. To achieve this operation, the seven latch units 10 through 70 are required.
In addition, when data is aligned according to the conventional method, three latch circuits are required for a 2-bit prefetch operation, fifteen latch circuits are required for an 8-bit prefetch operation, and ‘2n−1’ latch circuits are required for an n-bit prefetch operation (where n is an integer greater than 1).
However, a problem lies in that the number of latch circuits included in the conventional data alignment circuit rapidly increases as the number of prefetches increases when a memory chip operates in a fast operational mode. This is because the number of prefetches increases per unit time as the operational modes of the memory chip become faster.
In the conventional data alignment circuit, when the number of prefetches increases, the number of latch circuits required for data alignment is almost doubled. This leads to a problem in that a significant amount of area in the semiconductor chip layout is consumed by these latch circuits that serve the prefetch operations. Moreover, these problems may be further aggravated by high-speed operations by adversely affecting the semiconductor chip demand with increased power consumption needs.